LiFeどうでしょう

作業暫存

1.RLC and RRC : 才會動到VSZC裡的C值

2.期末CPU要可以跑投影片範例跟兩數除法

module top(in_a,in_b,cin,s0,s1,s2,overflow,out,cout);
input [7:0]in_a,in_b;
input cin,s0,s1,s2;
output overflow,cout;
output [7:0]out;
reg [7:0]out1,out2,cout1,cout2;

logic(in_a,in_b,s0,s1,out2,cout2);
arithmetic(in_a,in_b,cin,s0,s1,cout1,out1,overflow);
mux(out1,out2,cout1,cout2,s2,out,cout);

endmodule
//===================================================
module arithmetic(in_a,in_b,cin,s0,s1,cout,out,overflow);
input [7:0]in_a,in_b;
input s0,s1,cin;
output overflow,cout;
output [7:0]out;
reg [7:0]temp;
wire [6:0]t;

always@(s0||s1)
begin
if(s0==0&&s1==0)
temp = 8'b00000000;
else if(s0==1&&s1==0)
temp = in_b;
else if(s0==0&&s1==1)
temp = ~in_b;
else if(s0==1&&s1==1)
temp = 8'b11111111;
end

adder(out[0],t[0],cin,in_a[0],temp[0]);
adder(out[1],t[1],t[0],in_a[1],temp[1]);
adder(out[2],t[2],t[1],in_a[2],temp[2]);
adder(out[3],t[3],t[2],in_a[3],temp[3]);
adder(out[4],t[4],t[3],in_a[4],temp[4]);
adder(out[5],t[5],t[4],in_a[5],temp[5]);
adder(out[6],t[6],t[5],in_a[6],temp[6]);
adder(out[7],cout,t[6],in_a[7],temp[7]);
xor(overflow,t[6],cout);

endmodule
//===================================================
module adder(sum,out,cin,in_a,in_b);
input in_a,in_b,cin;
output sum,out;
wire t1,t2,t3;

and and1(t1,in_a,in_b);
xor xor1(t2,in_a,in_b);
and and2(t3,t2,cin);
or or1(out,t1,t3);
xor xor2(sum,t2,cin);

endmodule
//===================================================
module logic(in_a,in_b,s0,s1,out,cout);
input [7:0]in_a,in_b;
input s1,s0;
output [7:0]out,cout;
reg [7:0]out,cout;

always@(s0||s1)
begin
cout = 8'b00000000;
if(s0==0&&s1==0)
out = in_a&in_b;
else if(s0==1&&s1==0)
out = in_a|in_b;
else if(s0==0&&s1==1)
out = in_a^in_b;
else if(s0==1&&s1==1)
out = ~in_a;
end

endmodule
//===================================================
module mux(out1,out2,cout1,cout2,s2,out,cout);
input [7:0]out1,out2,cout1,cout2;
input s2;
output [7:0]out,cout;
reg [7:0]out,cout;

always@(s2||out1||out2)
begin
if(s2)
begin
out = out2;
cout = cout2;
end
else
begin
out = out1;
cout = cout1;
end
end

endmodule
//////=======================================
module top(carry,select,in,out,cout);
input [2:0]select;
input carry;
input [7:0]in;
output cout;
output [7:0]out;
reg [7:0]out;
reg cout;

always@(out)
begin
case(select)
3'b000:
begin
out = in;
cout = carry;
end
3'b001:
begin
out = {in[6:0],1'b0};
cout = carry;
end
3'b010:
begin
out = {0,in[7:1]};
cout = carry;
end
3'b011:
begin
out = 8'b00000000;
cout = carry;
end
3'b100:
begin
cout = in[7];
out = {in[6:0],carry};
end
3'b101:
begin
out = {in[6:0],in[7]};
cout = carry;
end
3'b110:
begin
out = {in[0],in[7:1]};
cout = carry;
end
3'b111:
begin
cout = in[0];
out = {carry,in[7:1]};
end
endcase
end

endmodule
/////======================================
module top(clk,carry,overflow,select,in,C,S,V,Z);
input [7:0]in;
input carry,clk,overflow;
input [3:0]select;
output C,S,V,Z;
reg t1,t2,t3,t4;
reg C,S,V,Z;

always@(negedge clk)
begin
t1 = carry;
t2 = in[7];
t3 = overflow;
if(in == 8'b00000000)
t4 = 1;
else
t4 = 0;
case(select)
4'b0001:
begin
Z = t4;
S = t2;
end
4'b0010:
begin
Z = t4;
S = t2;
C = t1;
V = t3;
end
4'b0101:
begin
Z = t4;
S = t2;
C = t1;
V = t3;
end
4'b0110:
begin
Z = t4;
S = t2;
end
4'b0111:
begin
Z = t4;
S = t2;
C = 0;
end
4'b1000:
begin
Z = t4;
S = t2;
end
4'b1010:
begin
Z = t4;
S = t2;
end
4'b1100:
begin
Z = t4;
S = t2;
end
4'b1110:
begin
Z = t4;
S = t2;
end
endcase
end
endmodule
///////================================================
module register(data,CLK,r1,r2,r3,r4,r5,r6,r7,load);
input [7:0]data;
input CLK;
input [6:0]load;
output [7:0]r1,r2,r3,r4,r5,r6,r7;
reg [7:0]r1,r2,r3,r4,r5,r6,r7;

always@(posedge CLK)
begin
    case(load)
        7'b1000000: r1=data;
        7'b0100000: r2=data;
        7'b0010000: r3=data;
        7'b0001000: r4=data;
        7'b0000100: r5=data;
        7'b0000010: r6=data;
        7'b0000001: r7=data;
    endcase
end
endmodule